With the continuous development of semiconductor technologies, feature size of metal-oxide-semiconductor (MOS) transistors has been reduced. Accordingly, the thickness of gate dielectric layers in the MOS transistors has become thinner and thinner. When a gate dielectric layer is overly thinned, however, various issues may occur. These issues may include time-related voltage breakdowns, hot carrier effects, and diffusion of impurities from the gate electrode toward the substrate. This can adversely affect stability and reliability of the formed transistors. Currently, use of SiO2 as a gate dielectric material may reach its physical limitation. Replacing SiO2 gate dielectric layer with high-k gate dielectric layer may significantly increase the physical thickness with the same effective oxide thickness (EOT) achieved to reduce leakage current of the gate electrode.
Most of high-k gate dielectric layers are made of metal oxides, which do not have fixed atomic coordinates. Compared with SiO2 gate dielectric material, high-k gate dielectric materials have much poorer bonding stability with the silicon substrate. Consequently, interfacial defects are formed between the high-k gate dielectric layer and the silicon substrate. The interfacial defects may be combined with oxygen to produce interstitial oxygen atoms and positively charged oxygen vacancies, which may further be combined with hydrogen to form unstable hydrogen bonds. Such unstable hydrogen bonds can cause a PMOS transistor to have negative bias temperature instability (NBTI). That is, at high temperatures and when the gate electrode is negatively biased, electrical parameter drift of the PMOS transistor may occur. On the other hand, the interstitial oxygen atoms and positively charged oxygen vacancies can cause an NMOS transistor to have positive bias temperature instability (PBTI). That is, at high temperatures and when the gate electrode is positively biased, electrical parameter drift of the NMOS transistor may occur.
Thus, there is a need to provide transistors with reduced NBTI and PBTI and methods for fabricating the transistors.